With the continuous scaling of the CMOS technology, the CMOS circuits are considered to be more tolerant to Single event Latchup (SEL) effects due to the reduction in the supply voltages. This paper reports the results from SEL testing performed on the first two prototypes for the new readout ASIC (SAMPA).
During RUN 3/RUN 4 at the Large Hadron Collider (LHC), the SAMPA chip will be used for the upgrade of read-out front end electronics of the ALICE (A Large Ion Collider Experiment) Time Projection Chamber (TPC) and Muon Chambers (MCH). The first prototype MPW1 and the second prototype V2 of the SAMPA chip were delivered in 2015 and 2016, respectively. The results are summarized from two different proton beam irradiation campaigns, conducted for SAMPA MPW1 and V2 prototypes at The Svedberg Laboratory (TSL) in Uppsala, and the Center of Advanced Radiation Technology (KVI) in Groningen, respectively.
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