This thesis covers the design, production and measurement of digital ultra-low voltage floating gate logic. The increasing demand for low-power electronics, fueled by the expanding market for portable devices and the growth of the Internet of things, both with a desire for longer battery life, enhances the importance of low-power logic styles in modern integrated circuit design. This leads to a rising demand for low-voltage design topologies because the simplest way to reduce both the static and dynamic power consumption is to reduce the supply voltage. The cost of this however is a severe penalty to the circuit speed. The ultra-low voltage (ULV) logic styles used in this thesis are designed to reduce gate delay and increase the circuit speed by utilizing capacitive coupling on the inputs to super-charge the gate terminal of critical transistors and thereby increase transistor current. The presented designs, simulations and measurements of the ULV logic prove the topology to be significantly faster than conventional electronics in ultra-low voltage operation. To demonstrate the high-speed qualities of ULV logic in hardware and compare its analog properties to conventional logic, a test circuit with an inverter from each topology is designed and manufactured. The ULV inverter used is from the 7th iteration ULV topology (ULV7) and is scaled to drive the capacitive load of a test setup. The conventional inverter is scaled equivalently and placed on the same chip. After production in Taiwan by TSMC using their 90nm Nexsys® process the finished chip produces measurements that show that the theorized and simulated qualities of ULV logic are highly applicable in silicon hardware implementations. The low propagation delay of the ULV logic makes it ideal for use in adder carry circuits. To utilize the ULV properties, new carry circuits are presented and simulated in this thesis, yielding results that prove them more energy efficient and significantly faster than conventional carry propagation circuits.