Robustness and Performance of Ultra Low Voltage logic

Abstract

In this thesis we will target mainly the operation of ULV circuits in order to impose factors that impact the behavior of low supply voltage circuits. Our main objective is to target the robustness of these circuits and imply as to what extent these circuits are improved. A new design for the enhancement in robustness is presented. Multiple-Valued logic scheme is addopted to achieve maximum performance. In addition Keeper transistor and their impact on performance is elaborated. In order to highlight the performance of these ULV circuits, we have implemented the presented design in a carry chain. The Process technology these circuits are simulated in, is TSMC 90nm. The transistor employed in circuits are of Low threshold voltage(LVT) type.