In this thesis there has been construct a standard cell library in 90nm CMOS technology meant for scientific and/or medical research purposes. This library is meant to operate on a supply voltage of 300mV, for example in order to improve the uptime of battery and solar cell powered devices, as well as be compatible with alternative power sources (heat, vibration, induction, etc). The performance variables for the library components were optimized with respect to delay, static power dissipation and robustness for ultra low voltage (ULV) operation. This has been done with a Multiobjective Optimization approach. The cells that have been optimized is a NOT, a NAND and a NOR gate. They have been used to design an XOR gate, a DFF and a D-LATCH. The three optimized cells and the XOR have been completed for synthesis. From these four cells, all types of digital logic can be synthesized. This has been shown with the synthesizing of a 32-bit adder. The 32-bit adder has been tested on 300mV and over several temperatures. Although operating circuits at low supply voltages offers advantages in terms of power and energy consumption, this method also introduces several problems such as increased delay variations and worsened noise margins. The simulations were preformed in a commercial 90nm process with high threshold cells. This was provided by TSMC. The simulations were carried out in Cadence Virtuoso Platform, Cadence Encounter RTL Compiler (encounter), Cadence Virtuoso Spectre and MatLab.