conversion. The study covers least significant bit-first (LSB), least significant bit-first with alternate bit inversion (LSB ABI) and most significant bit-first (MSB) digital input codes.
The serial cyclic D/A converters with LSB and LSB ABI input codes are implemented in a double-poly 0.35um AMS process. Measured results are provided and analyzed using standard static D/A converter performance measures. Circuits are tested using the practical radices 4, 8 and 16. Experimental results demonstrate that serial cyclic D/A converters using SFG inverters are feasible. Compared to related work on cyclic D/A conversion, the proposed circuits feature both a reduced number of devices and a reduction in the required die area.
Several new techniques are identified for extending the resolution beyond radix 4, 8 and 16 MVL applications. This includes an error correction algorithm called least significant bit-first with alternate bit inversion (LSB ABI), a sample and hold clock scheme and a Dual Data-Rate (DDR) mode of D/A converter operation. The techniques are implemented on a chip and measured results are provided.
The thesis also includes simulation work on several new SFG based circuits. A ternary serial D/A converter, a MSB-first serial D/A converter and a multiple-valued frequency divider which features re-configurable modulus.
Paper I: Jensen, R.Berg, Y. Serial Semi Floating Gate MOS D/A Converter With Configurable Resolution In IEEE TENCON 2004, vol. 4, pp. 254-257
Paper II: Configurable Serial-bit D/A Converter for Multiple Valued Logic In International Conference on Signals and Electronic Systems, ICSES 2004, September 13-15 2004, Poznan, Poland
Paper III: Jensen, R.; Berg, Y.; Lomsdalen, J.G.; Semi Floating-Gate S/H circuits IEEE NORCHIP 2005, pp. 76-179
Paper IV: Improved Serial SFG MOS D/A Converter with Configurable Resolution. In Proceedings of 5th IEEE Electronic Circuits and Systems Conference (ECS’05), 149-152, Bratislava, Slovakia, September 2005
Paper V: Jensen, Rene; Berg, Yngvar. Dual Data-Rate Cyclic D/A Converter Using Semi Floating- Gate Devices In IEEE ISMVL 2007, p. 37-37
Paper VI: Configurable MSB-first Serial D/A Converter using Semi Floating- Gate Devices In IEEE ICSES 2006
Paper VII: Recharged Comparator and Multiple-Valued N-ary Frequency Divider In 15th International Workshop on Post-Binary ULSI Systems, ULSIWS 2006, May 17, 2006, Nanyang Technological University, Singapore
Paper VIII: A Novel Ternary Switching Element Using CMOS Recharge Semi Floating-Gate Devices In Proceedings of hte 35th International Symposium on Multiple-Valued Logic, 19-21 May 2005 Pp. 54- 58