This thesis examines subthreshold operation for reducing power consumption and protection against power analysis attacks of digital CMOS circuits.
Subthreshold operation is considered the most efficient way to reduce the power consumption of CMOS. There are few studies analyzing the performance of sequencing elements in subthreshold region. Sequencing elements play an important part of clocked sequential circuit systems. Therefore, it is necessary to have a good understanding of the different design types and their applicability in subthreshold circuits.
In this thesis, different flip-flop designs commonly used in superthreshold systems are compared in subthreshold operation. According to process corner simulations, a PowerPC 603 type flip-flop operates successfully in all corners in a 65 nm process down to a power supply voltage of 125mV. This flip-flop has a delay time of 28.7 ns and a power consumption of 2.4 nW in the typical corner. The power consumption decrease corresponds to a reduction factor of 20 000, compared to normal operation.
As cryptographic algorithms have become more secure against cryptoanalysis attack, several types of attacks exploiting physical emitted informations have been reported. Power analysis attacks use the power consumption pattern to attack the chip. An increasing demand for secure data communication makes it even more important to design with resistance against side channel attacks in mind for certain applications.
Operating in subthreshold region significantly reduces the signal amplitude and the dynamic power consumption component. The reduction of these elements is used to create a S-box for the AES encryption cipher with increased resistance against power analysis attacks. By running with subthreshold operation, the correlation between power consumption of different input values decreases with a factor of 2 500 at the cost of 350 times delay degradation.
Simulations in 90 nm and 65 nm processes provided by STMicroelectronics are performed in Cadence Virtuoso Platform.