In an given system on chip the different IP cores have different capacity needs for communications. Given a fixed communication capacity between two or more IP cores and more than one set of communicating cores with different size for the capacity for communication. We will explore two different ways of generating an efficient network topology between arbitrary placed switches on the chip area.
The topology genereated assumes that the switching is static. There is also an attempt to genereate tables for routing based on Time Division Multiplexed Access (TDMA).
The thesis is written in norwegian.