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dc.contributor.authorVenckus, Bartas
dc.date.accessioned2019-11-13T23:45:42Z
dc.date.available2019-11-13T23:45:42Z
dc.date.issued2019
dc.identifier.citationVenckus, Bartas. Softcore HDL processor for implementation in FPGA and ASIC. Master thesis, University of Oslo, 2019
dc.identifier.urihttp://hdl.handle.net/10852/70824
dc.description.abstracteng
dc.language.isoeng
dc.subject
dc.titleSoftcore HDL processor for implementation in FPGA and ASICeng
dc.typeMaster thesis
dc.date.updated2019-11-13T23:45:42Z
dc.creator.authorVenckus, Bartas
dc.identifier.urnURN:NBN:no-73944
dc.type.documentMasteroppgave
dc.identifier.fulltextFulltext https://www.duo.uio.no/bitstream/handle/10852/70824/1/Bartas-Thesis.pdf


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