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A Programmable Hardware Calendar for High Resolution Pacing

Pontarelli, Salvatore; Bianchi, Giuseppe; Welzl, Michael
Chapter; AcceptedVersion; Peer reviewed
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hpsr18.pdf (265.1Kb)
Year
2018
Permanent link
http://urn.nb.no/URN:NBN:no-71903

CRIStin
1648488

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  • Institutt for informatikk [3604]
  • CRIStin høstingsarkiv [15923]
Original version
IEEE International Conference on High Performance Switching and Routing (HPSR) 2018. 2018, 1-6
Abstract
The challenge addressed in this paper consists in offloading packet-based pacing to a hardware Network Interface Card, while retaining the flexibility of software timers. In this direction, we propose, design, implement, and evaluate a hardware calendar, which can be programmed via a simple yet very flexible programming interface leveraging stateful (adaptive) per-packet timers. We show, for both specific examples (exponential, linearly increasing, etc) as well as for the general case, how to derive such a per-packet timer setting from a high-level desired rate envelope. Further, we describe and evaluate an FPGA implementation which relies on a novel insertion strategy for solving collisions in the calendar’s hash table.
 
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