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dc.contributor.authorElgesem, Ole Herman Schumacher
dc.date.accessioned2017-12-08T22:28:22Z
dc.date.available2017-12-08T22:28:22Z
dc.date.issued2017
dc.identifier.citationElgesem, Ole Herman Schumacher. Ultra Low Voltage Logic Design For High-Speed Processing. Master thesis, University of Oslo, 2017
dc.identifier.urihttp://hdl.handle.net/10852/59277
dc.description.abstractThis thesis presents the Ultra Low Voltage Dual Rail (ULVDR) logic style, a technology aimed at achieving high processing speeds at low supply voltage. Implementations of ULVDR inverters, NAND/NOR gates, XOR gates, and adders are shown. Useful simulations, principles, and guidelines for creating ULVDR circuits are introduced. When compared to equivalent circuits implemented in Cascode Voltage Switch Logic (CVSL), the ULVDR NAND gates were 57 times faster, ULVDR XOR gates were 28 times faster, and the ULVDR full-adder was 52 times faster. Simulations were done on long chains (30-32 elements) using a supply voltage of 300 mV. The increase in speed can enable new types of applications, where high processing speeds are essential, or allow lower power consumption by further decreasing supply voltage or putting circuits to sleep when done processing.eng
dc.language.isoeng
dc.subjectIoT.
dc.subjectgreen
dc.subjectultra-low voltage
dc.subjectripple-carry
dc.subjecthigh-speed
dc.subjectfull-adder
dc.subjectadder
dc.subjectlow-voltage
dc.subjectNAND
dc.subjectNOR
dc.subjectInternet of things
dc.subjectdual rail
dc.subjectCVSL
dc.subjectXOR
dc.subjectlogic
dc.subjectULVDR
dc.subjectULV
dc.titleUltra Low Voltage Logic Design For High-Speed Processingeng
dc.typeMaster thesis
dc.typeGroup thesis
dc.date.updated2017-12-08T22:28:21Z
dc.creator.authorElgesem, Ole Herman Schumacher
dc.identifier.urnURN:NBN:no-61969
dc.type.documentMasteroppgave
dc.type.documentGruppeoppgave
dc.identifier.fulltextFulltext https://www.duo.uio.no/bitstream/handle/10852/59277/1/olehelg_ULVDR_thesis.pdf


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