This thesis presents the Ultra Low Voltage Dual Rail (ULVDR) logic style, a technology aimed at achieving high processing speeds at low supply voltage. Implementations of ULVDR inverters, NAND/NOR gates, XOR gates, and adders are shown. Useful simulations, principles, and guidelines for creating ULVDR circuits are introduced. When compared to equivalent circuits implemented in Cascode Voltage Switch Logic (CVSL), the ULVDR NAND gates were 57 times faster, ULVDR XOR gates were 28 times faster, and the ULVDR full-adder was 52 times faster. Simulations were done on long chains (30-32 elements) using a supply voltage of 300 mV. The increase in speed can enable new types of applications, where high processing speeds are essential, or allow lower power consumption by further decreasing supply voltage or putting circuits to sleep when done processing.