Exploring the SEU Dependence on Supply Voltage scaling in 90 nm and 65 nm CMOS Flip-flops
AbstractDown-scaling of the supply voltage is considered as the most effective means of reducing the power- and energy consumption of integrated circuits (ICs). Reduction in the power- and energy consumption is highly beneficial in aerospace and defense applications that have a constrained power budget. These applications include, but are not necessarily limited to, payloads in solar powered spacecraft and rovers. The benefits that can be harvested from reducing the powerand energy consumption in such applications are reduced weight, reduced mass and/or increased functionality for a given power budget. Although supply voltage scaling can improve the energy efficiency of ICs, radiation induced errors also tend to increase with decreasing supply voltage. In order to enable reliable operation in radiation-rich environments, radiation induced errors must be mitigated, preferably with minimum area, power and performance penalties. In this thesis, the single event upset (SEU) dependence on supply voltage scaling is investigated for data flip-flops (DFFs) designed in 90 nm and 65 nm CMOS technology nodes. The radiation tolerance of the DFFs was characterized at supply voltages between 0.18 V and 1 V, and heavy ion radiation testing was performed using ions with linear energy transfer (LET) between 5:8 MeV-cm2=mg and 68:8 MeV-cm2=mg. Both temporal and spatial hardening techniques are utilized as a means of mitigating SEUs, and the impact of drive strength and sensitive node separation is evaluated. The examined circuit-level hardening techniques include triple modular redundancy (TMR), dual interlocked storage cell (DICE) and temporal dual-feedback (TDF), as well as inverter-based and current starved delay elements for SET filtering purposes. This study shows that radiation tolerant DFFs can offer soft error rate (SER) improvements of up to 55x, 121x and 600x, compared to a standard non-radiation tolerant DFF, when scaling the supply voltage down to 0.18 V, 0.25 V and 0.5 V, respectively. Simultaneously, by scaling the supply voltage down to 0.5 V and 0.25 V, radiation tolerant DFFs can achieve ~3.9x and ~12x higher energy efficiency, compared to when operating at a supply voltage of 1 V. Selective placement of high drive strength components showed to reduce the SEU sensitivity in DFFs by up to 112x, compared to DFFs utilizing standard drive strength. The impact of charge sharing was, on the other hand, increasingly challenging to mitigate with decreasing supply voltage. Nevertheless, based on the findings in this work, radiation tolerant DFFs operated at reduced supply voltage offer a clear advantage over standard non-radiation tolerant DFFs, and may therefore be suited for implementation in low power payloads, depending on the error rate requirements of the application. In addition to investigating the SEU dependence on supply voltage scaling, this thesis also presents the design and performance of subthreshold to above threshold level shifters, and the characterization of the proton beam properties at the Oslo Cyclotron Laboratory (OCL).
List of papers
|Paper I A. Hasanbegovic and S. Aunet, "Low-power subthreshold to above threshold level shifters in 90 nm and 65 nm process", Microprocessors and Microsystems (MICPRO), vol. 35, pp. 1-9, Feb. 2011. The paper is not available in DUO. The published version is available at: https://doi.org/10.1016/j.micpro.2010.11.003|
|Paper II A. Hasanbegovic and S. Aunet, "Proton beam characterization at Oslo cyclotron laboratory for radiation testing of electronic devices", IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS), pp. 135-140, Apr. 2013. The paper is not available in DUO. The published version is available at: https://doi.org/10.1109/DDECS.2013.6549805|
|Paper III A. Hasanbegovic and S. Aunet, "Supply voltage dependency on the single event upset susceptibility of temporal dual-feedback flip-flops in a 90 nm bulk CMOS process", IEEE Transactions on Nuclear Science (TNS), vol. 62, pp. 1888-1897, Aug. 2015. The paper is not available in DUO. The published version is available at: https://doi.org/10.1109/TNS.2015.2454479|
|Paper IV A. Hasanbegovi´c and S. Aunet, "Heavy ion characterization of temporal-, dual- and triple redundant flip-flops across a wide supply voltage range in a 65 nm bulk CMOS process", IEEE Transactions on Nuclear Science (TNS), vol. 63, pp. 2962-2970, Dec. 2016. The paper is not available in DUO. The published version is available at: https://doi.org/10.1109/TNS.2016.2614781|