As Moore s law continues, processors keep getting more cores packed together on the chip. This thesis is an empirical study of the rather newly introduced Intel Many Integrated Core (IMIC) architecture found in the Intel Xeon Phi. With roughly 60 cores connected by a high performance on-die interconnect, the Intel Xeon Phi makes an interesting candidate for High Performance Computing. By digging into parallel algorithms solving three well known problems, our goal is to optimize, test and compare run times with a regular Xeon processor. Results and their evaluations will be presented along the way, before a conclusion is drawn in the end. We also present limitations for the Intel Xeon Phi encountered from the tests.