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dc.date.accessioned2016-06-10T13:23:53Z
dc.date.available2016-06-10T13:23:53Z
dc.date.created2015-05-24T16:23:10Z
dc.date.issued2015
dc.identifier.citationMirmotahari, Omid Berg, Yngvar . Reliability of High Speed Ultra Low Voltage Differential CMOS Logic. Circuits and Systems. 2015, 6(5), 121-135
dc.identifier.urihttp://hdl.handle.net/10852/50461
dc.description.abstractIn this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are given. The results are obtained through Monte-Carlo simulations.en_US
dc.languageEN
dc.language.isoenen_US
dc.publisherScientific Research Publishing (SCIRP)
dc.rightsAttribution 4.0 International
dc.rights.urihttps://creativecommons.org/licenses/by/4.0/
dc.titleReliability of High Speed Ultra Low Voltage Differential CMOS Logicen_US
dc.typeJournal articleen_US
dc.creator.authorMirmotahari, Omid
dc.creator.authorBerg, Yngvar
cristin.unitcode185,15,5,40
cristin.unitnameNanoelektronikk
cristin.ispublishedtrue
cristin.fulltextoriginal
cristin.qualitycode1
dc.identifier.cristin1244200
dc.identifier.bibliographiccitationinfo:ofi/fmt:kev:mtx:ctx&ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.jtitle=Circuits and Systems&rft.volume=6&rft.spage=121&rft.date=2015
dc.identifier.jtitleCircuits and Systems
dc.identifier.volume6
dc.identifier.issue5
dc.identifier.startpage121
dc.identifier.endpage135
dc.identifier.doihttp://dx.doi.org/10.4236/cs.2015.65013
dc.identifier.urnURN:NBN:no-54051
dc.type.documentTidsskriftartikkelen_US
dc.type.peerreviewedPeer reviewed
dc.source.issn2153-1285
dc.identifier.fulltextFulltext https://www.duo.uio.no/bitstream/handle/10852/50461/1/CS_2015052214105529.pdf
dc.type.versionPublishedVersion


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