Abstract
The primary goals of this thesis was to design and implement a hardware friendly Zynq-based CGP algorithm and investigate the acceleration potential. It was made several attempts to find out if it was possible to increase the speed of the CGP algorithm by implementing single part of algorithm as hardware component. The Zynq-platform is a unique blend of two technologies, which includes a Dual ARM® Coretex-A9 Processer System and 7-series Programmable Logic. This means that Zynq is able to take advantage of software programming and in addition configure programmable hardware both at the same time.