There is an increasing need for sensitive, high perfomance sequence alignemnet tools. With the growing databases of scientificly analyzed protein sequences, more compute power is necessary. Specialized architectures arise, and a transition from serial to specialized implementationsis is required. This thesis is a study of whether Intel 60's cores Xeon Phi coprocessor is a suitable architecture for implementation of a sequence alignment tool. The performance relative to existing tools are evaluated, as well as measurements comparing the implementation to the theoretical peak performance of the architecture. SWIMIC, a sequence alignment tool utilizing the Smith-Waterman algorithm implemented for Intel's MIC (Many Integrated Core) architecture was made. It runs natively on a Xeon Phi coprocessor and is optimized with SIMD intrinsics, threading with OpenMP and pragma directives for vectorization. With potential memory and compute power unexploited, SWIMIC achieves 43 GCUPS, 74 % of a similar tool also running on the Xeon Phi, and 40 % of the leading tool running on CPU's. The study shows that the Xeon Phi coprocessor is not a suitable architecture to perform sequence alignments on, while utilizing the Smith-Waterman algorithm, due to relatively high memory footprint. The shared memory architecture possess a relatively small combined cache and with the lack of support for smaller data types this is a limitation that the four hardware thread and a 512 bit vector unit per core can not overcome.