This thesis explores different Single Event Latch-up (SEL) hardnesstechniques against radiation in a commercial 0.35µm technology fromAMS. Techniques like increasing nMOS to pMOS distance, guard rings,source to N-well/P-substrate contact distance, increasing N-well size,source/drain diffusion area, transistor width as well as relative transistor orientation are investigated and tested to achieve a high SEL threshold.Several structures holding these techniques are made in two differentoptions of AMS 0.35µm, one option with bulk (C35B4C3) and the otherwith an exitaxial layer (C35B4O1) in order to investigate the differences.The structures are based on the inverter in order to make the test structures as close to actual circuit design as possible. The inverter is also a favorable structure because it represents a worst case latch-up situation because of the parasitic components arising and the simple model needed to characterize it.The thesis also investigates whether using a pulsed laser module issuitable to investigate SEL susceptibility in favor of a particle accelerator.The structures were exposed to infrared (1064nm) laser pulses in order to emulate high energy particles striking the ASIC. The use of laser beam with a spot size of 2µm*2µm opened the possibility to choose which structure to expose with minimum impact on the nearby structures. By increasing the energy of the laser pulses, the SEL threshold of each structure could be determined by empirical testing.A digital input signal is propagated trough the structures in order toconﬁrm which structure experiences latch-up. A set of switches on the PCB is used to choose which structure to monitor. The current usage of the ASIC is monitored in order to detect latch-up and to log the latch-up current.Measurements presented a “threshold” distance between the contact and source of the transistors. If the contact-source distance is increased beyond 4.5µm the SEL threshold decreased about 70% in the epitaxial device. In the bulk device, if the contact-source distance was increased beyond 2.0µm the SEL threshold decreased to a level 12% beneath the reference structure.The most effective structure in the epitaxial device was the structurewith the N-well/P-substrate contacts placed in between the transistors.This structure presented a 30% decreased area and 87% higher thresholdthan the structure with the lowest threshold. Though, only 2.5% higherthreshold than second place and the same area.The most effective structure in the bulk device was the structure withnMOS source to pMOS source distance of 7.4 µm and the minimumN-well/P-substrate contact to source distance of 0.6µm. This structurepresented a 17% decreased area, a 465% higher SEL threshold and a 30%higher SEL current in comparison to the reference structure.