In 2004, the European Space Agency proposed a new Synthetic Aperture Radar mission, Wavemill, which would use new techniques to measure ocean height and ocean velocity down to 10 cm/s. Due to the high sampling frequency and the amount of data that would be produced, on-board processing would be necessary to more eﬃciently use the communication link, a link that would become a bottleneck if nothing was conducted on the data. An FPGA was recommended for performing the on-board processing. This thesis focuses on the implementation of a proposed SAR processor that will be used to process the raw SAR data in Wavemill. The SAR processor was synthesized for a Xilinx Virtex-6 FPGA and simulation veriﬁed the design for the range compression component. The synthesis showed that implementation of the proposed real-time SAR processor was possible. The synthesis also showed that the SAR processor would function with a clock frequency of minimum 240 MHz.