Thin films of transparent conductive oxides as active electrodes in combination with silicon substrates are pursued for new generation of solar cells. A main issue is to obtain structures with optimum interfacial properties in order to minimize charge carrier recombination and maximize cell efficiency. In this work we have investigated electronic properties and thermal stability of the interfacial states between indium tin oxide (ITO) and monocrystalline silicon. ITO films with thicknesses of 60 and 300 nm have been deposited by dc magnetron sputtering on n- and p-type (100) Si at room temperature. The samples were then annealed for 30 min at different temperatures in the range 100-600˚C. Current-voltage (IV), capacitance-voltage (CV) and deep-level transient spectroscopy (DLTS) have been used to electrically characterize the interface between ITO and Si. DLTS measurements on the samples with p-type Si reveal a dominant hole trap at around 0.37 eV above the valence band edge. In the n-type samples, several major electron traps have been observed in the range 0.1-0.2 eV below the conduction band edge. These electron traps are characterized by broad DLTS peaks indicating a broad band of the electronic energy levels rather than isolated point defect levels. All the traps in both p- and n-type samples are found to be located near the ITO-Si interface. Investigation of thermal stability of the observed electronic states has revealed that the dominant hole trap can be annealed out at 250˚C for 30 min, while the dominant electron traps can be stable up to 500˚C. IV and DLTS measurements demonstrate clear correlation between the annealing of the dominant electronic states and increase in the junction rectification.