low Voltage and Low Power Operational Amplifier

Abstract

Reducing the supply voltage of operational amplifers and analog circuitry in general, is of great importance as it will ensure the future coexistence of analog and digital circuits on the same silicon die. While digital circuits greatly benefit from the reduction in feature size and supply voltage, analog circuits on the other hand only beneft marginally because minimum size transistors cannot be used due to noise and offset requirements. This trend towards low voltage and low power, effects the fundamental limits of operational amplifiers. The gain and bandwidth are restricted by minimum voltages and currents. Also the dynamic range is degraded by these strict limits. Upwards, the dynamic range is lowered due to the reduced signal headroom as a result of reduced supply voltage. Downwards, the dynamic range is limited by larger noise voltages due to smaller supply currents. The only way to make the operational amplifer survive the trend towards lower supply voltages without deteriorate its characteristics, is by developing very effcient operational amplifer topologies that combines low voltage and low power operation and contemporary be as simple as possible to save die area. This thesis presents some of the main aspects of low voltage and low power operational amplifers and their ability to work from rail to rail on both input and output. The input referred offset voltage was also characterized. Theory around input and output stages are studied. A low voltage operational amplifer was processed in 0.35 um CMOS. Measurements were done on the operational amplifer and compared with the simulation results.