This master thesis discusses the VLSI implementation of an Analog VLSICochlea Model with an AER output interface. The cochlea uses a unidirectional filter cascade approach, and utilizes a capacitively coupled bi-quad filter section with three pseudo floating gate inverters as transconductance elements. The employed filter consumes very little power and the structure may be used to the effect of eliminating dc offset propagation errors. Simulation results are given along with functional descriptions of the circuit parts, and in some cases a mathematical treatment is included. The thesis includes a discussion on pseudo-floating gates (PFG) biasing-techniques, and a proposal for a future improvement is made. In the appendix a VerilogA model is described, showing a useful qualitative model of the reverse-biased diode below the reverse breakdown voltage. A system so multiple test circuits outputs can share a single output is also described in the appendix. In the introductory chapters a brief review on the workings of the mammal inner ear is also presented.