A coincidence processing unit in PET detectors separates single events (noise) from coincident events (positron events) to enhance the SNR of the final image and to lower the data rate in the transfer channel. This thesis describes the work carried out to design and implement a centralized coincidence processing unit for COMPET, a pre-clinical PET scanner with a novel geometry andread-out chain. In order to minimize the coincidence time resolution, a clock distribution scheme with phase correction has been implemented. For coincidence processing both a synchronous and asynchronous approach have been designed, implemented and tested, using point-to-point cabling and UDP/IP over 1 Gbps Ethernet respectively. Both implementations were done using a FPGA situated on a Xilinx development board. Results show that the synchronous solution handles coincidence rates of 1/4 of system clock frequency (100 MHz), with a coincidence time resolution of twice the system clock timeperiod. The asynchronous solution handles coincidence rates in the order of 5 Mcps with theoretically no upper limit on coincidence time resolution.