Evolvable hardware (EHW) is a method where hardware is designed and/or modified automatically by optimization algorithms called evolutionary algorithms (EAs). The results so far are promising but somewhat limited partly because of a scalability problem of the EHW design method. It is hard to generate circuits which are capable of handling large real-world problems in a competitive manner. Schemes for dealing with the scalability problem have been proposed earlier, however the application of these to run-time adaptive EHW systems has been limited. This thesis addresses the challenge to generate autonomous run-time adaptive digital EHW systems for solving large real-world problems. The challenge consists of dealing with the lack of scalability in EAs, combined with the challenge of designing an adaptive hardware architecture for the evolution. Specifically, hardware classifiers are developed for accurate classification of inputs with a large number of features. For experimentation with online adaptation, an on-chip evolutionary system has been proposed and implemented, making use of an on-chip processor. In order to overcome the scalability problem, the use of data buses and high-level building blocks has been investigated. Further, these elements have been combined with incremental evolution into a specialized high-speed classifier architecture for online evolution. The architecture has been applied to several difficult application benchmarks and compared to traditional approaches as well as previously presented EHW approaches. The work has resulted in a flexible system for on-chip evolution. The proposed online architecture is capable of classifying problems with a larger number of inputs than previous online EHW classifiers, and it gives a higher accuracy for these problems than previously presented EHW systems. These systems have often been based on offline evolution – regarded as less challenging than online evolution. In addition, the amount of evaluations needed for the evolutionary search is low compared to previously presented systems. The system has also shown to be competitive to traditional classification approaches for the applied benchmarks.
Paper I: A flexible on-chip evolution system implemented on a Xilinx Virtex-II Pro device
volume 3637 of LNCS, pages 66.75. Springer, 2005.
Paper II: On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition
First NASA/ESA Conference on Adaptive Hardware and Systems, 2006. AHS 2006.
pages 373-380. IEEE, 2006.
Paper III: Online Evolvable Pattern Recognition Hardware
Not yet available
(But this paper can work as a substitute:
An Online EHW Pattern Recognition System Applied to Face Image Recognition
volume 4448 of LNCS, pages 271-280. Springer, 2007.
Paper IV: Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA
Second NASA/ESA Conference on Adaptive Hardware and Systems, 2007. AHS 2007, pages 463-470. IEEE, 2007.
Paper V: An Online EHW Pattern Recognition System Applied to Sonar Spectrum Classification
volume 4684 of LNCS, pages 1-12. Springer, 2007.
Paper VI: Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control
NASA/ESA Conference on Adaptive Hardware and Systems, 2008. AHS '08, pages 32-39
Paper VII: A Comparison of Evolvable Hardware Architectures for Classification Tasks
volume 5216 of LNCS, pages 1-12. Springer, 2008.